odd verifying

用法例句

The system is of double clock design structure which makes the odd verifying circuit structure simple and easily effected.

系统采用双时钟设计结构,使得奇校验电路结构简单、易实现。

Nicety and continuity of data transfer are important performance indexes in serial communication system,usually certain error-tolerant technology is adopted,widely used are parity check,CRC,hamming code check and so on,but parity check can t checkout even code bits error,CRC-4 can only checkout 2 code bits error or correct 1 code bit.

数据传送的准确性和连贯性是串行通信系统的重要性能指标,通常采用一定的容错技术,广泛使用的有奇偶校验、CRC校验和海明码校验等,但奇偶校验无法检验出偶数个码元出错,CRC-4校验只能检错2位或纠错1位。

Based on the information hiding and the encryption protecting, and integrating the characteristic of the 24bit BMP image, this paper introduces a scheme that can dual protect the information transmission by first encrypting the information and then hiding the cryptograph in the 24bit BMP images with parity check hiding.

基于信息隐藏和加密两种技术 ,结合 2 4位 BMP图像文件格式的特点 ,提出一个采取对信息先加密 ,再把密文用奇偶校验隐藏到 2 4位 BMP图像文件的信息网上传送的双重保护机

Research on efficient triple disk failure tolerance data placement scheme based on parity code;

基于奇偶校验的三容错数据布局研究

To meet the need of high speed,least error and multitransmission in the serial communication by adopting the over-sample technology and a method of sequential circuit parity that is more effective and prompt than the traditional combined circuit,the design of dual channel UART used more conveniently is made.

为了满足串行通信中高速率、低错误率和多路传输的要求,通过采用过采样技术和一种比传统的组合逻辑电路快捷高效的时序电路奇偶校验方法,设计了使用更加灵活方便的双通道通用异步收发器(DUART)。

This paper introduces a faster and reliable checkpointing schema with N+1 parity by using cache and the incremental disk checkpointing technology.

本文运用缓冲区和增量有盘检查点相结合的技术提出了一个快速可靠的改进 N+1 奇偶校验检查点方案。

In view of the character that message in RAM has mutability when the RAM is subjected to interference,this paper discusses the concrete method of accomplishing odd-even check for out-of-chip data memory in SCM systems.

针对RAM受干扰时其中保存的信息易发生畸变的特点 ,论述了在单片机应用系统中对片外数据存储器实现奇偶校验的具体方法 ,对于设计单片机应用系统具有较高的指导作用和参考价值 。

Sometimes an eighth level is used for a parity character. Sometimes an eighth level is used for a parity check.

有时，它采用第8 层结构作奇偶校验。

Bit Interleaved Parity N code

比特间插奇偶校验N位码

Studies on Decoding and Application of Low-Density Parity-Check Codes;

低密度奇偶校验码译码研究及其应用

The FPGA Implement of Multi-Dimensional Concatenated Single Parity Check Codes;

多重级联奇偶校验码的FPGA实现

Research on Performance and Construction of Low-Density Parity-Check Codes;

低密度奇偶校验码的性能与构造研究

On Coding and Decoding of Low-Density Parity-Check Codes: Theory and Implementation;

低密度奇偶校验码编译码原理及实现

Low-density Parity-check Codes and Its Decoding Algorithm;

低密度奇偶校验码及其译码算法实现

A Frame Self-Synchronization Method for Low-Density Parity Check Code

一种低密度奇偶校验码帧自同步方法

Analysis of loop removal from finite-length LDPC codes

有限长低密度奇偶校验码的去环分析

FAULT DETECTION BASED ON PARITY CHECKS IN PETRI NET CONTROLLER

基于奇偶校验的Petri网控制器故障检测

Redundant characters often work as checking devices, as in parity and other checks.

冗余字符通常用作校验手段,如奇偶校验或其它校验。

On boundary regions filling, a new even-odd check algorithm is presented.

描述了一个新的区域奇偶校验填充算法.

Research on Low-Density Parity-Check Codes and Their Applications in Parallel Concatenation Structure;

低密度奇偶校验码及其并行级联构造的研究

On Applications of Low Density Parity-Check Codes in DAMB and VWDK Systems;

低密度奇偶校验码在DAMB和VWDK系统中的应用研究

Research on LDPC Decoding Algorithm and Hardware Implementation;

低密度奇偶校验码译码算法研究及实现

Study on Implementation of a Class of Low-Density Parity-Check Code Based on FPGA;

一类低密度奇偶校验码的研究及FPGA实现

Study and Implementation of Low Density Parity Check Codes Encoding and Decoding Algorithm;

低密度奇偶校验码编/译算法的研究与实现

Distributed computer system of taking even-odd check as multicomputer communication;

以奇偶校验位为标识的分布式计算机系统